`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg validout_r;
reg [4:0]out_r;
reg [15:0]d_r;
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		out_r<=5'd0;
		validout_r<=1'b0;
        d_r<=16'd0;
	end
	else begin
		if(sel==2'b00)begin
			out_r<=5'd0;
			validout_r<=1'b0;
            d_r<=d;
		end
		else if(sel==2'b01)begin
			out_r<={1'b0,d_r[3:0]}+{1'b0,d_r[7:4]};
			validout_r<=1'b1;
            d_r<=d_r;
		end
        else if(sel==2'b10)begin
			out_r<={1'b0,d_r[3:0]}+{1'b0,d_r[11:8]};
			validout_r<=1'b1;
            d_r<=d_r;
		end
		else begin
			out_r<={1'b0,d_r[3:0]}+{1'b0,d_r[15:12]};
			validout_r<=1'b1;
            d_r<=d_r;
		end
	end
end
assign out=out_r;
assign validout=validout_r;

//*************code***********//
endmodule